Demo 4: Resource Allocations in Tiled Architectures

In this demo, the problem we solve is to determine where memory controllers should be placed on chip and how network links and buffers should be allocated to interconnect processors and memory controllers so as to maximize performance. Details of the problem and formulation can be found in Chapter 6 of Optimization and Mathematical Modeling in Computer Architecture.




Case Study 4

Case Study 4:
Resource Allocation in Tiled Architectures

Generating custom instruction candidates from an application is the process of analyzing the intermediate representation of the program, and finding subgraphs which can be made into instructions.

Select from the following basic blocks.




Relative tolerance gap: within % of optimal




Problem to be submitted:

Solver Status:
Solver Output: